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| KS0118C INTRODUCTION The KS0118C is a CMOS integrated circuit designed for the GEN LOCK and ND Conversion. It is a Monolithic IC that enabled an analog NTSC composite video signal to digitize at a clock rate that is synchronized and locked to the incoming video horizontal line frequency. It includes clamping function, 8-bit digitizing and creation of a line locked sampling clock. It is possible to correspond to the video signal system of LDP by the use of KA9413, KA 9414-D ICS together, which is designed for the Digital Video Signal Processor. 80-QFP-1420C GENLOCK ADC ORDERING IN FORMATION Device KS0118C Package 80-QFP-1420C Operating Temperature -20I~+75I FEATURES * * * * * * * * * * * NTSC Video Signal Input Line-locked Sync and Clock Generation Line to Line Jitter < 20 nsec O Differential Gain 2% Differential Phase 2 Programmable Sample Clock Frequency from 25 to 30 MHz Built-in 8 Bit CMOS Analog to Digital Converter Programmable Gain Control and Automatic DC Offset Control for Video Signal Input Programmable PLL Time Constants for Tracking Different Input Types Correctly Tracks Line Drop-outs Provides a Microprocessor 3 Wire Serial Interface Built-in Decimation Filter Single Power Supply: +5V KS0118C BLOCK DIAGRAM GENLOCK ADC VIN 70 CLAMP 8 BIT ADC LPF DECIMATION FILTER 48 55 CVBS<0:7> DIGITAL OFFSET CONTROL 35 SYNC DETECTOR OUTPUT TIMING 39 40 LOCK VS SLICE XTL1 XTL2 4 5 CRYSTAL DRIVER DTO JITTER REDUCTION PIXEL COUNTER PHASE DET/ PLL FILTER SERIAL MICOM INTERFACE 16 FSMP 19 25 27 SFRS SCLK SDAT Fig. 1 KS0118C PIN CONFIGURATION CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 VDD (A) GENLOCK ADC GND GND VDD VDD GND NC NC NC NC VDD NC NC NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC 40 SLICE 39 VS 38 NC 37 NC 36 NC 35 LOCK 34 NC 33 NC 32 NC 31 NC 30 NC 29 NC 28 NC 27 SDAT 26 NC 25 SCLK NC VRB VRT CREF1 VDD (A) CAGC VIN GND NC RREF GND VDD (A) RVCO CREF2 GND NC NC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 KS0118 1 2 3 NC 4 XTL1 5 XTL2 6 VDD (A) 7 VDD (A) 8 GND 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GND FSMP NC SFRS SYG FRZ VDD LDP NC NC NC NC NC NC NC RCPLL RSTB Fig. 2 KS0118C PIN DESCRIPTION Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol RCPLL RSTB NC XTL1 XTL2 VDD(A) VDD(A) GND NC NC SYG NC FRZ VDD GND FSMP LDP NC SFRS NC NC NC NC NC SCLK NC SDAT NC NC NC NC NC NC NC LOCK NC NC NC VS SLICE I/O I/O I I O O I O I I I I/O O O O Description GENLOCK ADC External Filter Pin for Analog PLL System Reset Signal Input (Active Low) No Connection Pin1 for External Crystal Oscillator Pin2 for External Crystal Oscillator + 5V Supply Voltage for Analog Domain + 5V Supply Voltage for Analog Domain Ground No Connection No Connection Line Locked Horizontal Sync Signal No Connection Connect this Pin to + 5V for proper Operation + 5V Supply Voltage for Digital Domain Ground Freq. & Phase compensated Sample Clock used for ADC Connect this Pin to + 5V for proper Operation No Connection Frame Signal for Serial Data Interface No Connection No Connection No Connection No Connection No Connection Clock Signal Input for Serial Data Interface No Connection Serial Data in Serial Interface No Connection No Connection No Connection No Connection No Connection No Connection No Connection High when the GENLOCK is locked & in Tracking State No Connection No Connection No Connection Vertical Sync Signal Output Sync level. Low when CVBS < 32. This Signal is not Line locked KS0118C PIN DESCRIPTION (Continued) Pin No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol NC NC NC NC NC VDD GND CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 GND VDD VDD VDD(A) GND NC NC NC NC VRB VRT CREF1 VDD(A) CAGC VIN GND NC RREF GND VDD(A) RVCO CREF2 GND NC NC I/O O O O O O O O O I/O I/O I/O I I I/O I/O I/O Description No Connection No Connection No Connection No Connection No Connection + 5V Supply Voltage for Digital Domain Ground 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal 8 Bit Composite Video Baseband Signal Ground + 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain + 5V Supply Voltage for Digital Domain Ground No Connection No Connection No Connection No Connection Bottom Voltage Reference for ADC Top Voltage Reference for ADC Decoupling Pin for Reference Voltage +5V Supply Voltage for Analog Domain Capacitor for Offset Control Analog NTSC Video Signal Input (1Vpp) Ground No Connection Current Setting Pin for Internal Analog Circuitry Ground + 5V Supply Voltage for Analog Domain Current Setting Pin for Analog VCO Decoupling Pin for Reference Voltage Ground No Connection No Connection GENLOCK ADC KS0118C ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Voltage on any Digital Pin Operating Temperature Storage Temperature Symbol VDD VPIN T OPR T STG Value -0.5 ~+7.0 GND ~ VDD - 20 ~ + 75 -55 ~ +125 GENLOCK ADC Unit V V I I ELECTRICAL CHARACTERISTICS (Ta = 25I, unless otherwise specified) Characteristic Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Static Power Current Dynamic Power Current Serial uP I/O Set-up Time Serial uP I/O Hold Time Differential Phase Differential Gain Signal to Noise Ratio uP Maximum Data Rate Frequency Lock Range Symbol VIH VIL VOH VOL lCCS ICCD tUS tUH DP DG SNR fMPU FLT VDD = 4.75V XTL = 24.576MHz Test Conditions VDD = 4.75V VDD = 5.25V VDD = 4.75V VDD = 5.25V VDD = 5.25V VDD = 5.25V XTL = 24.576MHz XTL = 24.576MHz Min 4.0 4.0 34 140 35 5.0 28.60 Typ 74 2.0 2.0 Max 1.0 1.0 94 200 10 10 28.66 Unit V V V mA mA mA ns ns deg % dB MHz MHz KS0118C TEST CIRCUIT VDD(A) VDD GENLOCK ADC VDD GND 0.1} VDD(A) 0.1 200 0.1 V25 VDD(A) 22 VIN 15} 10 + + 0.1 + GND 22 GND + 0.1 22 22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 0.1 65 0.1 66 67 68 69 70 71 120 72 73 0.1 VDD(A) + 2.4K 74 75 76 8K 77 78 79 3nF 80 1 1K 10K 33pF 0.1uF 2 3 4 5 6 7 8 KS0118 30 29 28 27 26 25 22 V11 0.1 82 30K 33pF 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 0.1uF 22uF + + GND RTSB X-TAL 24.576MHz 22uF FSMP GND VDD GND GND VDD(A) V DD Fig. 3. KS0118C APPLICATION INFORMATION FUNCTION DESCRIPTION GENLOCK ADC 1. GENERAL DESCRIPTION The KS0118C implements the funtions of an 8 Bit ADC, Analog Clamp, Analog PLL Clock Generator and Digital Timing Generation. Throuth the use of VLSl technology, the KS0118C combines analog circuits with digital signal processing to obtain locking characteristics not achievable by ordinary methods. The KS0118C uses 1 external frequency reference to create many different programmable line lock sampling clocks. 2. ANALOG TO DIGITAL CONVERTER The KS0118C uses a two step, 8 bit and auto zero ADC to digitize the analog video input. The VRT and VRB pins are the top and bottom reference voltage for the ADC. These references are generated internally but required 0.1O decoupling capacitors to ground. 3. EXTERNAL FREQUENCY REFERENCE The KS0118C requires an external stable frequency reference to generate the sampling clock. Although a wide range of frequency will work with the GENLOCK, it is recommended that 24.576MHz be used as the reference. This can be derived from a standard crystal or an external clock. 4. ANALOG PHASE LOCK LOOP The KS0118C has an internal PLL used for producing the sampling clock. This PLL requires an external loop filter at pin 1 (RCPLL) as shown in the application circuit. The ground connections for this filter should be placed close to pin 78, while the inputs should be located close to pin 1. The PLL also requires an external resistor to converter the voltage of the RCPLL node to a current for use by the internal VCO. The voltage of the pin 76 (RVCO) will track RCPLL Although the absolute voltage of these pins depends on many factors, it will be between 0.75 and 4.50 voltalge. The voltage will exhibit the standard characteristics of an analog PLL. KS0118C GENLOCK ADC VIN FSMP CVBS tDD SLICE tDSLICE VS tDSVS Fig. 4 Data Path Propagation Delay and Key Timing Signals ~ ~ WHITE LEVEL CODE = 224.234 100IRE 160 ( 170 ) CODES BLANK LEVEL CODE = 84 40 IRE Fig. 5 Digitized Code Levels ~~ ~~ ADC CODE = 32 tDSYS ~ ~ KS0118C APPLICATION CIRCUIT KS9411 KA9413 GENLOCK ADC VDD(A) VDD VDD 0.1 + GND 0.1} VDD(A) 0.1 200 0.1 V25 Composit Video Signal input ( 1Vpp ) from KA9411 120 VDD(A) 22 15} 10 + + + GND 22 GND + 0.1 22 22 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 40 39 38 37 36 35 34 33 32 31 KS9411 KA9413 0.1 0.1 0.1 VDD(A) 2.4K 74 75 76 8K 77 78 79 3nF 80 1 1K 10K 33pF 0.1uF 2 3 4 5 6 7 8 KS0118 30 29 28 27 26 25 22 V11 0.1 82 30K 33pF 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 0.1uF 22uF + + GND 22uF X-TAL GND 24.576MHz GND VDD(A) VDD GND VDD KS9411 KA9413 |
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